Development of Information-Control Interface for Communication of Spacecraft Units
DOI:
https://doi.org/10.22213/2413-1172-2020-2-91-99Keywords:
antenna control unit, FPGA programming, information-control interface, data transfer protocolAbstract
The paper presents the development of a Protocol for simple and reliable data transmission for the antenna control unit in harsh operating conditions. The logical level of the Protocol is implemented on the FPGA based on the HDLC Protocol. The physical data link is a redundant, galvanically coupled interface with a bipolar self-synchronizing Manchester-II code.
The relevance of developing the Protocol is the introduction of a domestic elemental base that is resistant to harsh environmental impacts, including radiation, the degree of importance of the development of the space industry as a whole, and the spheres that depend on it.
The paper discusses the purpose of the antenna control unit. The necessity of developing a Protocol for information and control interface for the control unit is justified. A review of scientific and technical information on the components of this Protocol is conducted. The physical, channel, and information levels of the developed Protocol are considered. The implementation of the channel and information layer in the Verilog HDL language for FPGAs is also presented.
The QuartusII program has developed a program code that implements the channel and information levels of data transmission based on the Protocol of information and control interface of the antenna control unit with the computer unit. After that, a circuit design is formed from individual code blocks, where input and output signals are set for the blocks.
Data transfer Protocol modeling was performed in the ModelSim-Altera debugging environment and the development board. The simulation confirmed the correctness of the chosen solutions in the process of creating the data transfer Protocol. The correct response receipt with two bytes of checksum was received for the specified command. The transmitted data is equal to the received data, and the checksum for receiving and transmitting is equal to each other.
Developers can accept the material presented in this scientific paper as the basis for implementing data exchange between technical devices, for which the issue of saving FPGA resources is acute.References
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